U.S. Pat. Nos. 3,504,457 and 3,499,250 describe the use of poromeric materials, specifically polyurethane reinforced by polyester fiber, for the polishing of semiconductor wafers. In the years since these patents were issued, the described materials have become the generally accepted standard for preparing the surface of silicon wafers.
Silicon wafers are the substrates upon which electronic devices known as integrated circuits are built. Typically, ingots of monocrystalline silicon are sliced into thin wafers 0.015 to 0.025 inches thick. The wafers are then usually lapped to make them flat and subsequently chemically etched. After etching, the wafers are subjected to a process known in the industry as polishing. Machines used for polishing are similar to machines used for lapping. In the polishing process, wafers are affixed to the polishing machine and then brought into rubbing contact with one or more poromeric materials which have been adhered to the rotating lapping plate. During the polishing process, the poromeric pad material is kept saturated with an alkaline suspension containing fine particles of silica. The alkaline suspension (slurry) reacts chemically with the silicon atoms on the surface of the wafer to produce a reaction product which is somewhat softer than the underlying silicon. Once the reaction product has formed on the wafer surface, further reaction is inhibited. During the polishing process, the reaction product is continually wiped away causing fresh silicon to be exposed to the effects of the slurry.
The function of the polishing pad is to act both as a carrier of the slurry and as a wipe to effect the removal of the reaction product from the wafer surface. It can be easily understood that the final shape or geometry of the wafer surface will be greatly affected by the manner in which the polishing pad exposes fresh silicon for reaction. Areas of the wafer in firmest contact with the pad will be wiped most vigorously and thus react most quickly. In these areas, silicon material will appear to be "polished away" most rapidly. If, for example, the pad is relatively soft and compliant, it will conform more easily to the wafer's contours and produce a softer ultimate shape with rounded edges. If, on the other hand, the pad is very hard, it will produce a flatter wafer with sharper edges.
At the time U.S. Pat. No. 3,504,457 was issued (Apr. 7, 1970), the state-of-the art required polished silicon wafers with rounded edges. The specified geometry of the polished wafer was several orders of magnitude less demanding than it is today. Further, the wafer polishing technology was still in the early stages of development and many different polishing techniques were used. Therefore, the requirement was for the soft, resilient polishing pads described in the above patents. Such soft pads made the polishing process relatively forgiving.
Recent developments in very large scale integrated circuit (VLSI) technology have brought much more stringent requirements for surface quality and the overall flatness and geometric precision of the wafer. Edge rounding is now accomplished by other means so that the function of the pad can be limited to creating as flat a surface as possible.